The present invention relates generally to silicon wafer processing, and more particularly, to devices for holding silicon wafers as they are subjected to ion bombardment and to heat treatment.
Various techniques are known for processing silicon wafers to form devices, such as integrated circuits. One technique includes implanting oxygen ions into a silicon wafer to form buried layer devices known as silicon-on-insulator (SOI) devices. In these devices, a buried insulation layer is formed beneath a thin surface silicon film. These devices have a number of potential advantages over conventional silicon devices (e.g., higher speed performance, higher temperature performance and increased radiation hardness). The lesser volume of electrically active semiconductor material in SOI devices, as compared with bulk silicon devices, tends to reduce parasitic effects such as leakage capacitance, resistance, and radiation sensitivity.
In one known technique, known by the acronym SIMOX, a thin layer of a monocrystalline silicon substrate is separated from the bulk of the substrate by implanting oxygen ions into the substrate to form a buried dielectric layer. This technique of xe2x80x9cseparation by implanted oxygenxe2x80x9d (SIMOX), provides a heterostructure in which a buried silicon dioxide layer serves as a highly effective insulator for surface layer electronic devices.
In the SIMOX process, oxygen ions are implanted into silicon, after which the material is annealed to form the buried silicon dioxide layer or BOX region. The annealing phase redistributes the oxygen ions such that the silicon/silicon dioxide boundaries become more abrupt, thus forming a sharp and well-defined BOX region, and heals damage in the surface silicon layer caused by the ion bombardment.
During the SIMOX process, the wafers are subjected to relatively severe conditions. For example, the wafers are typically heated to temperatures of about 500-600 degrees Celsius during the ion implantation process. Subsequent annealing temperatures are typically greater then 1000 degrees Celsius. In contrast, most conventional ion implantation techniques do not tolerate temperatures greater than 100 degrees Celsius. In addition, the implanted ion dose for SIMOX wafers is in the order of 1xc3x971018 ions per square centimeter, which can be two or three orders of magnitude greater than some known techniques.
Conventional wafer-holding devices are often incapable of withstanding the relatively high temperatures associated with SIMOX processing. Besides the extreme temperature conditions, in rotatable ion implantation systems a secure wafer gripping problem arises. Furthermore, wafer-holding structures having exposed metal are ill-suited for SIMOX processes because the ion beam will induce sputtering of the metal and, thus, result in wafer contamination. In addition, the structure may deform asymmetrically due to thermal expansion, which can damage the wafer surface and/or edge during high temperature annealing so as to compromise wafer integrity and render it unusable.
Another disadvantage associated with certain known wafer holders is electrical discharge of the wafers. If a wafer holder is formed from electrically insulative materials, the wafer will become charged as it is exposed to the ion beam. The charge build up disrupts the implantation process by stripping the ion beam of space charge neutralizing electrons. The charge built-up on the wafer can also result in a discharge to a nearby structure via an electrical arc, which can also contaminate the wafer or otherwise damage it.
Another disadvantage associated with conventional wafer holders in rotatable ion implantation systems is the lack of secure and efficient wafer gripping. Failure to secure a wafer against the centrifugal forces that are present in a rotatable system can result in damage to the wafer. If a wafer is not precisely placed and secured in the wafer holder, the wafer can fall out of the wafer holder assembly or otherwise be damaged during the load, unload, and ion implantation process.
Even when the wafer is held secure, many techniques cause other damage to the wafer during the ion implantation process. For example, holding pins can crush when securing the wafer causing localized thermal drifts much like a heat sink thus damaging wafer integrity. Wafer-holding pins formed of hard materials can leave marks on the wafer, yet pins formed of soft materials can stick to the wafer; neither situation is desirable.
Mears et al. (U.S. Pat. No. 4,817,556) discloses a device for holding a wafer. Mears utilizes a collet containing a plurality of fingers that apply lateral pressure to the edge surface of the wafer. Mears teaches contacting the entire edge of the wafer, and does not disclose the importance of reducing the contact area. The fingers of the Mears device are flush against the edge of the wafer, which increases the contact area, and can result in electrical arcing between the finger and the wafer. Particularly, any voids (microscopic or otherwise) in the finger/wafer contact area, can initiate an electrostatic discharge that can damage the wafer.
Another disadvantage associated with some existing wafer holders is shadowing. Shadowing is encountered when wafer holder structures obstruct the path of the ion beam, and thereby prevent implantation of the shadowed wafer regions. This deprivation of usable wafer surface area is a common problem in wafer holders that do not reduce the profile of their structural components.
It would, therefore, be desirable to provide a wafer holder that is able to withstand the relatively high temperatures and energy levels associated with SIMOX wafer processing while also reducing the potential for sputter contamination. In addition, it would be desirable to provide a wafer-holding pin that reduces arcing, reduces shadowing, and provides a simpler wafer-gripping capability.
The present invention provides a polymeric wafer-holding structures that maintain their structural integrity and prevent the build up of electrical charge on the wafer during high temperature semiconductor processing. Although thermoset polymeric materials have been generally thought to be incompatible with semiconductor fabrication processes that are carried out at a high temperatures, e.g., about 250 C, it has been discovered that thermoset polymers, when placed in service under vacuum conditions, can actually withstand temperatures of 600 C, or higher, without degradation.
Although the invention is primarily shown and described in conjunction with SIMOX wafer processing, it is understood that the wafer-holding pin has other applications relating to implanting ions into a substrate and to wafer processing in general.
In one aspect of the invention, a wafer-holding pin formed from a thermosetting resin material is disclosed and can be used to hold a wafer in a vacuum environment at a temperature of between about 250 C and about 650 C. The thermoset material is able to withstand an oxygen ion beam without substantial oxidation. The pin has distal and proximal portions, and the distal one can be adapted to hold the wafer via a groove that is sized and shaped to receive an edge of the wafer. The proximal portion is adapted to couple with a wafer-holding assembly.
More specifically, the pins of the present invention can have distal portion that includes a head coupled to a flange with a wafer-receiving groove therebetween. The groove is adapted to engage an edge of the wafer and has an inner surface that is at least partially cylindrical in shape. The inner surface can exhibit a radial symmetry about an axis for an azimuthal angle of at least 45 degrees.
In a further aspect of the invention, the wafer-holding pin provides a conductive path from the wafer to the assembly, which can be coupled to ground. By grounding the wafer, any build up of electrical charge on the wafer is inhibited for preventing potentially damaging electrical arcing from the wafer during the ion implantation process. In an exemplary embodiment, the pin is filled with an electrically conductive material, for example, carbon. The material provides electrical conductivity for the wafer-holding pin to achieve optimal SIMOX wafer processing conditions.
In yet another aspect of the invention, the wafer-holding pins have a geometry that is effective to reduce the likelihood of electrical discharges from the wafer. In one embodiment, the pins have a proximal portion for coupling to a distal end of wafer-holding arms in a wafer-holding assembly and a distal portion for holding the wafer. In one embodiment, the distal portions have an arcuate wafer-receiving neck disposed between a wedge-shaped upper region and a tapered surface. The geometry of the pin upper region reduces the amount of pin material proximate the wafer so as to reduce the likelihood of electrical arcing between the wafer and the pin during the ion implantation.
In another aspect of the invention, the wafer-holding pins have a geometry that reduces the need for precise alignment and provides a simpler wafer gripping capability. These pins facilitate wafer placement into the wafer holder, and pin coupling to the wafer holder assembly. In one embodiment, the pins have a proximal portion for coupling to a base structure of the wafer-holding assembly, and a distal portion for holding the wafer. The distal end of the pin is further defined by having a longitudinal axis extending from the distal portion towards the proximal end. The distal portion is at least partially radially symmetric about the longitudinal axis (or a line parallel thereto), and has a wafer-receiving groove disposed between a head and a flange. The wafer-receiving groove preferably contacts only the top and bottom of the wafer edge.
Due to the cylindrical symmetry of the distal portion, the need for precise pin alignment with the wafer is relaxed. The pins are able to engage a wafer across a much wider angle of approach. Thus, the radial symmetry reduces the need for precision in aligning the pins when they are attached to the other elements of the wafer-holding assembly.
In addition, the wafer-receiving groove contacts top and bottom regions of the wafer edge such that the area of the pin in contact with the wafer edge is reduced. This reduces arcing between the wafer edge and the pin during the ion implantation process.
The geometry of the head of the distal portion can also be effective in reducing the pin profile, by reducing the amount of pin material proximate the wafer. This has the effect of reducing not only arcing but also shadowing, thereby facilitating ion implantation of the entire wafer surface area.
In a further aspect of the invention, an ion implanter with a wafer-holding assembly uses a pin comprised of a thermosetting resin material suitable for use in a vacuum environment operating at a temperature of about 250 C to about 650 C, and is able to withstand an oxygen ion beam without substantial oxidization.